.TH lepton-netlist 1 "@DATE@" "Lepton EDA" @VERSION@
.SH NAME
lepton-netlist - Lepton EDA Netlist Extraction and Generation
.SH SYNOPSIS
.B lepton-netlist
[\fIOPTION\fR ...] [\fB-g\fR \fIBACKEND\fR | \fB-f\fR \fIFILE\fR] [\fI--\fR] \fIFILE\fR ...

.SH DESCRIPTION
.PP

\fBlepton-netlist\fR is a netlist extraction and generation tool, and is
part of the Lepton EDA (Electronic Design Automation) toolset.  It takes
one or more electronic schematics as input, and outputs a netlist.  A
netlist is a machine-interpretable description of the way that
components in an electronic circuit are connected together, and is
commonly used as the input to a PCB layout program such as
\fBpcb\fR(1) or to a simulator such as \fBgnucap\fR(1).

A normal \fBlepton-netlist\fR run is carried out in two steps.  First, the
\fBlepton-netlist\fR frontend loads the specified human-readable schematic
\fIFILE\fRs, and compiles them to an in-memory netlist description.
Next, a `backend' is used to export the connection and component data
to one of many supported netlist formats.

\fBlepton-netlist\fR is extensible, using the Scheme programming language.

.SH GENERAL OPTIONS
.TP 8
\fB-q\fR, \fB--quiet\fR
Quiet mode. Turns off all warnings/notes/messages.
.TP 8
\fB-v\fR, \fB--verbose\fR
Verbose mode.  Output all diagnostic information.
.TP 8
\fB-L\fR, \fB--lepton-path\fR=\fIDIRECTORY\fR
Prepend \fIDIRECTORY\fR to the list of directories to be searched
for Scheme files.  It is done before loading and/or evaluating any
Scheme code.  This option can be specified multiple times.
.TP 8
\fB-g\fR, \fB--backend\fR=\fIBACKEND\fR
Specify the netlist backend to be used.
.TP 8
\fB-f\fR, \fB--file-backend\fR=\fIFILE\fR
Load and use netlist backend from \fIFILE\fR.
\fIFILE\fR is expected to have name like "gnet-NAME.scm" and contain entry
point function NAME (where NAME is the backend's name).
.TP 8
\fB-O\fR, \fB--backend-option\fR=\fISTRING\fR
Pass an option string to the backend.
.TP 8
\fB-b\fR, \fB--list-backends\fR
Print a list of available netlist backends.
.TP 8
\fB-o\fR, \fB--output\fR=\fIFILE\fR
Specify the filename for the generated netlist.  By default, output is
directed to `output.net'.
If `-' is given instead of a filename, the output is directed to the
standard output.
.TP 8
\fB-l\fR, \fB--pre-load\fR=\fIFILE\fR
Specify a Scheme file to be loaded before the backend is loaded or
executed.  This option can be specified multiple times.
.TP 8
\fB-m\fR, \fB--post-load\fR=\fIFILE\fR
Specify a Scheme file to be loaded between loading the backend and
executing it.  This option can be specified multiple times.
.TP 8
\fB-c\fR, \fB--eval-code\fR=\fIEXPR\fR
Specify a Scheme expression to be executed during \fBlepton-netlist\fR
startup.  This option can be specified multiple times.
.TP 8
\fB-i\fR, \fB--interactive\fR
After the schematic files have been loaded and compiled, and after all
Scheme files have been loaded, but before running the backend, enter a
Scheme read-eval-print loop.
.TP 8
\fB-h\fR, \fB--help\fR
Print a help message.
.TP 8
\fB-V\fR, \fB--version\fR
Print \fBlepton-netlist\fR version information.
.TP 8
\fB--\fR
Treat all remaining arguments as schematic filenames.  Use this if you
have a schematic filename which begins with `-'.

.SH BACKENDS
.PP
Currently, \fBlepton-netlist\fR includes the following backends:

.TP 8
\fBallegro\fR
Allegro netlist format.
.TP 8
\fBbae\fR
Bartels Autoengineer netlist format.
.TP 8
\fBbom\fR, \fBbom2\fR
Bill of materials generation.
.TP 8
\fBcalay\fR
Calay netlist format.
.TP 8
\fBcascade\fR
RF Cascade netlist format
.TP 8
\fBdrc\fR, \fBdrc2\fR
Design rule checkers (\fBdrc2\fR is recommended).
.TP 8
\fBeagle\fR
Eagle netlist format.
.TP 8
\fBewnet\fR
Netlist format for National Instruments ULTIboard layout tool.
.TP 8
\fBfuturenet2\fR
Futurenet2 netlist format.
.TP 8
\fBgeda\fR
Native gEDA netlist format (mainly used for testing and diagnostics).
.TP 8
\fBgossip\fR
Gossip netlist format.
.TP 8
\fBgsch2pcb\fR
Backend used for \fBpcb\fR(1) file layout generation by
\fBgsch2pcb\fR(1).  It is not recommended to use this backend
directly.
.TP 8
\fBliquidpcb\fR
LiquidPCB netlist format.
.TP 8
\fBmathematica\fR
Netlister for analytical circuit solving using Mathematica.
.TP 8
\fBmaxascii\fR
MAXASCII netlist format.
.TP 8
\fBosmond\fR
Osmond netlist format.
.TP 8
\fBpads\fR
PADS netlist format.
.TP 8
\fBpartslist1\fR, \fBpartslist2\fR, \fBpartslist3\fR
Bill of materials generation backends (alternatives to \fBbom\fR and
\fBbom2\fR).
.TP 8
\fBPCB\fR
\fBpcb\fR(1) netlist format.
.TP 8
\fBpcbpins\fR
Generates a \fBpcb\fR(1) action file for forward annotating pin/pad
names from schematic to layout.
.TP 8
\fBprotelII\fR
Protel II netlist format.
.TP 8
\fBredac\fR
RACAL-REDAC netlist format.
.TP 8
\fBspice\fR, \fBspice-sdb\fR
SPICE-compatible netlist format (\fBspice-sdb\fR is recommended).
Suitable for use with \fBgnucap\fR(1).
.TP 8
\fBswitcap\fR
SWITCAP switched capacitor simulator netlist format.
.TP 8
\fBsystemc\fR
Structural SystemC code generation.
.TP 8
\fBtango\fR
Tango netlist format.
.TP 8
\fBtEDAx\fR
Trivial EDA eXchange (tEDAx) format.
.TP 8
\fBvams\fR
VHDL-AMS code generation.
.TP 8
\fBverilog\fR
Verilog code generation.
.TP 8
\fBvhdl\fR
VHDL code generation.
.TP 8
\fBvipec\fR
ViPEC Network Analyser netlist format.


.SH EXAMPLES
.PP
These examples assume that you have a `stack_1.sch' in the current directory.
.PP
\fBlepton-netlist\fR requires that at least one schematic to be specified on the
command line:

.nf
	./lepton-netlist stack_1.sch
.ad b

.PP
This is not very useful since it does not direct \fBlepton-netlist\fR to do
anything.
.PP
Specify a backend name with `\-g' to get \fBlepton-netlist\fR to output a
netlist:

.nf
	./lepton-netlist \-g geda stack_1.sch
.ad b

.PP
The netlist output will be written to a file called `output.net'
in the current working directory.

.PP
You can specify the output filename by using the `\-o' option:

.nf
	./lepton-netlist \-g geda stack_1.sch \-o /tmp/stack.netlist
.ad b

.PP
Output will now be directed to `/tmp/stack.netlist'.

.PP
You could run (for example) the `spice-sdb' backend against the
schematic if you specified `\-g spice-sdb', or you could generate a
bill of materials for the schematic using `\-g partslist1'.

.PP
To obtain a Scheme prompt to run Scheme expressions directly, you can
use the `\-i' option.

.nf
	./lepton-netlist \-i stack_1.sch
.ad b

.PP
\fBlepton-netlist\fR will load `stack_1.sh', and then enter an interactive
Scheme read-eval-print loop.

.SH AUTHORS
See the `AUTHORS' file included with this program.

.SH COPYRIGHT
.nf
Copyright \(co 2012-2017 gEDA Contributors.
Copyright \(co 2017-@YEAR@ Lepton Developers.
License GPLv2+: GNU GPL version 2 or later. Please see the `COPYING'
file included with this program for full details.
.PP
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.

.SH SEE ALSO
\fBlepton-schematic\fR(1), \fBlepton-symcheck\fR(1), \fBpcb\fR(1), \fBgnucap\fR(1)
